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» Large Event Traces in Parallel Performance Analysis
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ICPP
2002
IEEE
15 years 6 months ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
CLUSTER
2009
IEEE
14 years 11 months ago
Coordinating the use of GPU and CPU for improving performance of compute intensive applications
GPUs have recently evolved into very fast parallel co-processors capable of executing general purpose computations extremely efficiently. At the same time, multi-core CPUs evolutio...
George Teodoro, Rafael Sachetto Oliveira, Olcay Se...
IPPS
2006
IEEE
15 years 7 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
IROS
2007
IEEE
122views Robotics» more  IROS 2007»
15 years 7 months ago
Design of a new spatial 3-DOF parallel mechanism with application to a PDP TV mounting device
—In this paper, we propose a new 3-DOF parallel mechanism for PDP TV mounting device with 2-rotation and 1-translation. The most important operational requirement of this device ...
Jae Heon Chung, Byung-Ju Yi, Sung Oh
HPDC
2008
IEEE
15 years 7 months ago
The performance of bags-of-tasks in large-scale distributed systems
Ever more scientists are employing large-scale distributed systems such as grids for their computational work, instead of tightly coupled high-performance computing systems. Howev...
Alexandru Iosup, Omer Ozan Sonmez, Shanny Anoep, D...