656 search results - page 26 / 132 » Large-Graph Layout Algorithms at Work: An Experimental Study |
75
Voted
DAC
2001
ACM
15 years 10 months ago
2001
ACM
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
ICASSP
2008
IEEE
15 years 4 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
96
Voted
CASES
2010
ACM
14 years 7 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
Power densities have been increasing rapidly at all levels of server systems. To counter the high temperatures resulting from these densities, systems researchers have recently st...
UIST
2003
ACM
15 years 2 months ago
2003
ACM
Recent work is beginning to reveal the potential of numerical optimization as an approach to generating interfaces and displays. Optimization-based approaches can often allow a mi...