Most FPGA technology mapping approaches either target Lookup Tables (LUTs) or relatively simple Programmable Logic Blocks (PLBs). Considering networks of PLBs during technology map...
Sean Safarpour, Andreas G. Veneris, Gregg Baeckler...
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negat...
We give a tight lower bound of ( n) for the randomized one-way communication complexity of the Boolean Hidden Matching Problem [BJK04]. Since there is a quantum one-way communica...