87 search results - page 7 / 18 » Latency Minimization for Synchronous Data Flow Graphs |
ARVLSI
1995
IEEE
15 years 3 months ago
1995
IEEE
A new method of retiming plesiochronous data is described. This method features latency of less than a cell-time and requires only minimal support circuitry. No flow control or ha...
148
click to vote
VDA
2010
15 years 2 months ago
2010
While there have been intensive efforts in developing better 3D flow visualization techniques, little attention has been paid to the design of better user interfaces and more effe...
111
click to vote
DAC
2003
ACM
16 years 23 days ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
105
click to vote
EUROPAR
2009
Springer
15 years 3 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
116
click to vote
ASPDAC
1999
ACM
15 years 4 months ago
1999
ACM
: This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow gr...