87 search results - page 9 / 18 » Latency Minimization for Synchronous Data Flow Graphs |
ICCAD
1994
IEEE
15 years 3 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
101
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INFOVIS
2005
IEEE
15 years 5 months ago
2005
IEEE
Cartographers have long used flow maps to show the movement of objects from one location to another, such as the number of people in a migration, the amount of goods being traded,...
DAC
2006
ACM
16 years 22 days ago
2006
ACM
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
101
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ISCA
1995
IEEE
15 years 3 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
102
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ISSS
1999
IEEE
15 years 4 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...