636 search results - page 109 / 128 » Latency Performance of SOAP Implementations |
105
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IEEEPACT
2005
IEEE
15 years 5 months ago
2005
IEEE
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
104
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CJ
2006
14 years 11 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
102
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ASPLOS
2011
ACM
14 years 3 months ago
2011
ACM
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
103
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MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...