Sciweavers

636 search results - page 33 / 128
» Latency Performance of SOAP Implementations
Sort
View
FPL
2006
Springer
129views Hardware» more  FPL 2006»
15 years 3 months ago
Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
Florian Stock, Andreas Koch
DAC
2006
ACM
16 years 22 days ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
TCAD
2010
168views more  TCAD 2010»
14 years 6 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
ICPP
2005
IEEE
15 years 5 months ago
LiMIC: Support for High-Performance MPI Intra-node Communication on Linux Cluster
High performance intra-node communication support for MPI applications is critical for achieving best performance from clusters of SMP workstations. Present day MPI stacks cannot ...
Hyun-Wook Jin, Sayantan Sur, Lei Chai, Dhabaleswar...
AINA
2009
IEEE
15 years 6 months ago
Modeling Multiprocessor Cache Protocol Impact on MPI Performance
This paper presents a modeling method particularly suited to analyze interactions between Message Passing Interface MPI library execution and distributed cache coherence protocol....
Ghassan Chehaibar, Meriem Zidouni, Radu Mateescu