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129
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FPL
2006
Springer
129views Hardware» more  FPL 2006»
15 years 7 months ago
Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...
Florian Stock, Andreas Koch
DAC
2006
ACM
16 years 4 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
189
Voted
TCAD
2010
168views more  TCAD 2010»
14 years 10 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
133
Voted
ICPP
2005
IEEE
15 years 9 months ago
LiMIC: Support for High-Performance MPI Intra-node Communication on Linux Cluster
High performance intra-node communication support for MPI applications is critical for achieving best performance from clusters of SMP workstations. Present day MPI stacks cannot ...
Hyun-Wook Jin, Sayantan Sur, Lei Chai, Dhabaleswar...
135
Voted
AINA
2009
IEEE
15 years 10 months ago
Modeling Multiprocessor Cache Protocol Impact on MPI Performance
This paper presents a modeling method particularly suited to analyze interactions between Message Passing Interface MPI library execution and distributed cache coherence protocol....
Ghassan Chehaibar, Meriem Zidouni, Radu Mateescu