Sciweavers

636 search results - page 48 / 128
» Latency Performance of SOAP Implementations
Sort
View
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 5 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 5 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
CN
1998
81views more  CN 1998»
14 years 11 months ago
Improving the WWW: Caching or Multicast?
We consider two schemes for the distributionof Web documents. In the first scheme the sender repeatedly transmits the Web document into a multicast address, and receivers asynchr...
Pablo Rodriguez, Keith W. Ross, Ernst Biersack
TII
2008
77views more  TII 2008»
14 years 11 months ago
The One-Shot Task Model for Robust Real-Time Embedded Control Systems
Embedded control systems are often implemented in small microprocessors enabled with real-time technology. In this context, control laws are often designed according to discrete-ti...
Camilo Lozoya, Manel Velasco, Pau Martí
IJPP
2010
137views more  IJPP 2010»
14 years 10 months ago
Parallel Option Price Valuations with the Explicit Finite Difference Method
Abstract. We show how computations such as those involved in American or European-style option price valuations with the explicit finite difference method can be performed in par...
Alexandros V. Gerbessiotis