636 search results - page 57 / 128 » Latency Performance of SOAP Implementations |
116
click to vote
CF
2006
ACM
15 years 5 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
HOTI
2002
IEEE
15 years 4 months ago
2002
IEEE
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
IPPS
1998
IEEE
15 years 4 months ago
1998
IEEE
We show how the traditional protocol stack, such as TCP/IP, can be eliminated for socket based high speed communication within a cluster. The SCI shared memory interconnect is used...
HPCA
2003
IEEE
16 years 5 days ago
2003
IEEE
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...
GLOBECOM
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...