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MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
15 years 5 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
15 years 5 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
PIMRC
2010
IEEE
14 years 9 months ago
Low-complexity iteration control for MIMO-BICM systems
Air bandwidth is a precious resource for wireless communication. Multiple-antenna (MIMO) systems enable an increase in channel capacity without increasing the air bandwidth. An ite...
C. Gimmler, Timo Lehnigk-Emden, Norbert Wehn
ICC
2007
IEEE
102views Communications» more  ICC 2007»
15 years 6 months ago
Distributed Scheduling in Input Queued Switches
— Dealing with RTTs (Round Trip Time) in IQ switches has been recently recognized as a challenging problem, especially if considering distributed (multi-chip) scheduler implement...
Alessandra Scicchitano, Andrea Bianco, Paolo Giacc...
TPDS
2010
115views more  TPDS 2010»
14 years 10 months ago
Providing QoS with the Deficit Table Scheduler
—A key component for networks with Quality of Service (QoS) support is the egress link scheduling algorithm. An ideal scheduling algorithm implemented in a high-performance netwo...
Raul Martinez-Morais, Francisco J. Alfaro-Cortes, ...