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» Latency Performance of SOAP Implementations
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134
Voted
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 8 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
163
Voted
DEBS
2010
ACM
15 years 7 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
146
Voted
CCS
2010
ACM
15 years 3 months ago
TASTY: tool for automating secure two-party computations
Secure two-party computation allows two untrusting parties to jointly compute an arbitrary function on their respective private inputs while revealing no information beyond the ou...
Wilko Henecka, Stefan Kögl, Ahmad-Reza Sadegh...
123
Voted
WWW
2003
ACM
16 years 4 months ago
A Light-weight, Temporary File System for Large-scale Web Servers
Several recent studies have pointed out that file I/Os can be a major performance bottleneck for some large Web servers. Large I/O buffer caches often do not work effectively for ...
Dong Li, Jun Wang
124
Voted
IROS
2009
IEEE
173views Robotics» more  IROS 2009»
15 years 10 months ago
Biologically inspired compliant control of a monopod designed for highly dynamic applications
— In this paper the compliant low level control of a biologically inspired control architecture suited for bipedal dynamic walking robots is presented. It consists of elastic mec...
Sebastian Blank, Thomas Wahl, Tobias Luksch, Karst...