3 search results - page 1 / 1 » Layer minimization of escape routing in area array packaging |
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. ...
106
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ICCAD
2008
IEEE
15 years 7 months ago
2008
IEEE
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
125
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FPGA
2003
ACM
15 years 6 months ago
2003
ACM
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...