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ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
15 years 5 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ANCS
2006
ACM
15 years 5 months ago
Design of a web switch in a reconfigurable platform
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In...
Christoforos Kachris, Stamatis Vassiliadis
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
15 years 6 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind
FPL
2003
Springer
136views Hardware» more  FPL 2003»
15 years 5 months ago
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
Roland Höller
NOMS
2002
IEEE
130views Communications» more  NOMS 2002»
15 years 4 months ago
Design of a network level management information model for automatically switched transport networks
The concept of Automatically Switched Transport Networks (ASTN) combines elements of distributed connection management from the IP world with classical transport network functiona...
Georg Lehr, Ulrike Hartmer, Ralf Geerdsen