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» Layered Switching for Networks on Chip
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IEEEIAS
2008
IEEE
15 years 6 months ago
COTraSE: Connection Oriented Traceback in Switched Ethernet
Layer 2 traceback is an important component of end-toend packet traceback. Whilst IP traceback identifies the origin network, L2 traceback extends the process to provide a more ...
Marios S. Andreou, Aad P. A. van Moorsel
FPL
2008
Springer
110views Hardware» more  FPL 2008»
15 years 1 months ago
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
Matthew Shelburne, Cameron Patterson, Peter Athana...
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 5 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
CCR
2006
92views more  CCR 2006»
14 years 11 months ago
Flow labelled IP over ATM: design and rationale
We describe a system in which layer 2 switching is placed directly under the control of layer 3 routing protocols on a hop-by-hop basis. Specifically, ATM switching is controlled ...
Greg Minshall, Robert M. Hinden, Eric Hoffman, Fon...
RTAS
1997
IEEE
15 years 4 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford