Sciweavers

248 search results - page 26 / 50
» Layered Switching for Networks on Chip
Sort
View
FPL
2003
Springer
100views Hardware» more  FPL 2003»
15 years 5 months ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
15 years 5 months ago
Micro-Network for SoC: Implementation of a 32-Port SPIN network
We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 G...
Adrijean Andriahantenaina, Alain Greiner
INFOCOM
2007
IEEE
15 years 6 months ago
A Cross-Layer Architecture to Exploit Multi-Channel Diversity with a Single Transceiver
—The design of multi-channel multi-hop wireless mesh networks is centered around the way nodes synchronize when they need to communicate. However, existing designs are confined ...
Jay A. Patel, Haiyun Luo, Indranil Gupta
ICPPW
2000
IEEE
15 years 4 months ago
Challenges in URL Switching for Implementing Globally Distributed Web Sites
URL, or layer-5, switches can be used to implement locally and globally distributed web sites. URL switches must be able to exploit knowledge of server load and content (e.g., of ...
Zornitza Genova, Kenneth J. Christensen
INFOCOM
2003
IEEE
15 years 5 months ago
The effect of layer-2 store-and-forward devices on per-hop capacity estimation
— Tools such as pathchar, clink, and pchar attempt to measure the capacity of every Layer-3 (L3) hop in a network path. These tools use the same underlying measurement methodolog...
Ravi Prasad, Constantinos Dovrolis, Bruce A. Mah