248 search results - page 31 / 50 » Layered Switching for Networks on Chip |
140
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VLSID
2010
IEEE
15 years 5 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
130
Voted
NOCS
2009
IEEE
15 years 8 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
106
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CN
2008
15 years 1 months ago
2008
Electrical-to-optical domain conversions and vice versa (denoted by O/E/O conversions) for each hop in optical core transport networks impose considerable capital and financial ov...
114
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INFOCOM
1996
IEEE
15 years 6 months ago
1996
IEEE
A number of proposals for supporting IP over ATM are under discussion in the networking community including: LAN emulation, classical IP over ATM, routing over large clouds, and m...
125
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TRIDENTCOM
2010
IEEE
14 years 11 months ago
2010
IEEE
Within the framework of the BONE European Network of Excellence, we setup a multi-domain multi-layer testbed covering three different networks at two distinct locations in Europe. ...