248 search results - page 35 / 50 » Layered Switching for Networks on Chip |
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
AHS
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
ISCA
2010
IEEE
15 years 4 months ago
2010
IEEE
Cloud computing is a disruptive trend that is changing the way we use computers. The key underlying technology in cloud infrastructures is virtualization – so much so that many ...
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GECCO
2009
Springer
15 years 6 months ago
2009
Springer
The paper deals with optimization of collective communications on multistage interconnection networks (MINs). In the experimental work, unidirectional MINs like Omega, Butterfly a...
HOTI
2002
IEEE
15 years 4 months ago
2002
IEEE
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...