248 search results - page 3 / 50 » Layered Switching for Networks on Chip |
209
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
168
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
160
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DATE
2000
IEEE
15 years 10 months ago
2000
IEEE
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
156
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NOCS
2008
IEEE
16 years 5 days ago
2008
IEEE
Abstract— In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach i...
150
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ASAP
2003
IEEE
15 years 11 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...