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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 3 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
BROADNETS
2006
IEEE
15 years 5 months ago
Intra and Interdomain Circuit Provisioning Using the OSCARS Reservation System
— With the advent of service sensitive applications such as remote controlled experiments, time constrained massive data transfers, and video-conferencing, it has become apparent...
Chin Guok, David W. Robertson, Mary R. Thompson, J...
ISPASS
2009
IEEE
15 years 6 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
105
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ISPASS
2006
IEEE
15 years 5 months ago
Modeling TCAM power for next generation network devices
Applications in Computer Networks often require high throughput access to large data structures for lookup and classification. Many advanced algorithms exist to speed these searc...
Banit Agrawal, Timothy Sherwood
ICNP
1998
IEEE
15 years 3 months ago
A Class of End-to-End Congestion Control Algorithms for the Internet
We formulate end-to-end congestion control as a global optimization problem. Based on this formulation, a class of minimum cost flow control (MCFC) algorithms for adjusting sessio...
S. Jamaloddin Golestani, S. Bhattacharyya