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SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
15 years 6 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
IEICET
2007
58views more  IEICET 2007»
14 years 11 months ago
On Constraints for Path Computation in Multi-Layer Switched Networks
Bijan Jabbari, Shujia Gong, Eiji Oki
119
Voted
AICT
2005
IEEE
138views Communications» more  AICT 2005»
15 years 5 months ago
A Layered Architecture for Supporting Optical Burst Switching
This paper defines a new layered architecture for supporting optical burst switching in an optical core network. The architecture takes into account both the control plane as well...
Farid Farahmand, Jason P. Jue, Vinod Vokkarane, Jo...
81
Voted
ANOR
2008
112views more  ANOR 2008»
14 years 11 months ago
Analysis of a tandem network model of a single-router Network-on-Chip
We study a single-router Network-on-Chip modelled as a tandem queueing network. The first node is a geoK /D/1 queue (K fixed) representing a network interface, and the second node...
Paul Beekhuizen, Dee Denteneer, Ivo J. B. F. Adan
122
Voted
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
15 years 3 months ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin