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ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
15 years 8 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He
DAC
2002
ACM
16 years 24 days ago
Analysis of power consumption on switch fabrics in network routers
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
Terry Tao Ye, Giovanni De Micheli, Luca Benini
SDL
2003
147views Hardware» more  SDL 2003»
15 years 1 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
15 years 6 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
LCN
2007
IEEE
15 years 6 months ago
A Scalable Hybrid Approach to Switching in Metro Ethernet Networks
—The most common technology in Local Area Networks is the Ethernet protocol. The continuing evolution of Ethernet has propelled it into the scope of Metropolitan Area Networks. E...
Minh Huynh, Prasant Mohapatra