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75
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DATE
2005
IEEE
108views Hardware» more  DATE 2005»
15 years 3 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
15 years 3 months ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
15 years 1 months ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram
73
Voted
AUTOMATICA
2007
48views more  AUTOMATICA 2007»
14 years 9 months ago
Interconnection of port-Hamiltonian systems and composition of Dirac structures
Port-based network modeling of physical systems leads to a model class of nonlinear systems known as port-Hamiltonian systems. Port-Hamiltonian systems are defined with respect t...
J. Cervera, A. J. van der Schaft, Alfonso Ba&ntild...