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150
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EURODAC
1995
IEEE
164views VHDL» more  EURODAC 1995»
15 years 7 months ago
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
Srimat T. Chakradhar, Anand Raghunathan
122
Voted
DAC
2003
ACM
16 years 4 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
163
Voted
SIGSOFT
2010
ACM
15 years 1 months ago
Community-based, collaborative testing and analysis
This article proposes a research agenda aimed at enabling optimized testing and analysis processes and tools to support component-based software development communities. We hypoth...
Atif M. Memon, Adam A. Porter, Alan Sussman
EWRL
2008
15 years 5 months ago
Efficient Reinforcement Learning in Parameterized Models: Discrete Parameter Case
We consider reinforcement learning in the parameterized setup, where the model is known to belong to a parameterized family of Markov Decision Processes (MDPs). We further impose ...
Kirill Dyagilev, Shie Mannor, Nahum Shimkin
CEC
2009
IEEE
15 years 7 months ago
Automatic system identification based on coevolution of models and tests
In evolutionary robotics, controllers are often designed in simulation, then transferred onto the real system. Nevertheless, when no accurate model is available, controller transfe...
Sylvain Koos, Jean-Baptiste Mouret, Stéphan...