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DATE
2005
IEEE
99views Hardware» more  DATE 2005»
15 years 4 months ago
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
Irith Pomeranz, Sudhakar M. Reddy
ATS
2003
IEEE
93views Hardware» more  ATS 2003»
15 years 3 months ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
15 years 2 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
VTS
1998
IEEE
124views Hardware» more  VTS 1998»
15 years 2 months ago
A Test Pattern Generation Methodology for Low-Power Consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
INLG
2010
Springer
14 years 8 months ago
Generating Natural Language Descriptions of Z Test Cases
Critical software most often requires an independent validation and verification (IVV). IVV is usually performed by domain experts, who are not familiar with specific, many times ...
Maximiliano Cristiá, Brian Plüss