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» Lectures on VLSI and Integrated Circuit Design
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GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
15 years 3 months ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
90
Voted
ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
15 years 3 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
CHINAF
2006
110views more  CHINAF 2006»
14 years 9 months ago
Time-domain analysis methodology for large-scale RLC circuits and its applications
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...
Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong ...
86
Voted
SBCCI
2004
ACM
134views VLSI» more  SBCCI 2004»
15 years 2 months ago
An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage s...
Gabriella Trucco, Giorgio Boselli, Valentino Liber...
IJCV
1998
81views more  IJCV 1998»
14 years 9 months ago
Estimating the Focus of Expansion in Analog VLSI
In the course of designing an integrated system for locating the focus of expansion (FOE) from a sequence of images taken while a camera is translating, a variety of direct motion ...
Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung...