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» Lectures on VLSI and Integrated Circuit Design
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GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh
SBCCI
2004
ACM
100views VLSI» more  SBCCI 2004»
15 years 2 months ago
Design of RF CMOS low noise amplifiers using a current based MOSFET model
This paper presents a design methodology for RF CMOS Low Noise Amplifiers (LNA). This methodology uses a current–based MOSFET model, which allows a detailed analysis of an LNA f...
Virgínia Helena Varotto Baroncini, Oscar da...
92
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DFT
1999
IEEE
131views VLSI» more  DFT 1999»
15 years 1 months ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
15 years 6 months ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
15 years 3 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen