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» Lectures on VLSI and Integrated Circuit Design
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GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
15 years 3 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
SLIP
2005
ACM
15 years 5 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
CDES
2006
107views Hardware» more  CDES 2006»
15 years 1 months ago
An Algorithm for Yield Improvement via Local Positioning and Resizing
The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been ...
Vazgen Karapetyan
GLVLSI
2007
IEEE
106views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Floorplan repair using dynamic whitespace management
We describe an efficient, top-down strategy for overlap removal and floorplan repair which repairs overlaps in floorplans produced by placement algorithms or rough floorplanni...
Kristofer Vorwerk, Andrew A. Kennings, Doris T. Ch...
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
15 years 5 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden