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SIGARCH
2008
96views more  SIGARCH 2008»
14 years 9 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 2 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
ACSAC
2000
IEEE
15 years 2 months ago
Enabling Secure On-Line DNS Dynamic Update
Domain Name System (DNS) is the system for the mapping between easily memorizable host names and their IP addresses. Due to its criticality, security extensions to DNS have been p...
Xunhua Wang, Yih Huang, Yvo Desmedt, David Rine
BMCBI
2006
124views more  BMCBI 2006»
14 years 9 months ago
The development and validation of the Virtual Tissue Matrix, a software application that facilitates the review of tissue microa
Background: The Tissue Microarray (TMA) facilitates high-throughput analysis of hundreds of tissue specimens simultaneously. However, bottlenecks in the storage and manipulation o...
Catherine M. Conway, Deirdre O'Shea, Sallyann O'Br...
EGH
2003
Springer
15 years 2 months ago
Automatic shader level of detail
Current graphics hardware can render procedurally shaded objects in real-time. However, due to resource and performance limitations, interactive shaders can not yet approach the c...
Marc Olano, Bob Kuehne, Maryann Simmons