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» Level Shifter Design for Low Power Applications
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AIA
2007
14 years 11 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann
IPCCC
2006
IEEE
15 years 3 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
SCCC
1998
IEEE
15 years 2 months ago
Resurrecting Ada's Rendez-Vous in Java
Java is a programming language designed with concurrency in mind from its inception. However, the synchronization mechanism provided is a restricted version of Hoare's Monito...
Luis Mateu, José M. Piquer, Juan Leó...
SBCCI
2005
ACM
122views VLSI» more  SBCCI 2005»
15 years 3 months ago
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Cavigl...
GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
15 years 3 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis