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» Level Shifter Design for Low Power Applications
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PDP
2011
IEEE
14 years 1 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
15 years 6 months ago
Double-gate SOI devices for low-power and high-performance applications
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhop...
CODES
2006
IEEE
15 years 3 months ago
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) alo...
Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nali...
VLSISP
2008
104views more  VLSISP 2008»
14 years 9 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...
PC
2007
161views Management» more  PC 2007»
14 years 9 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...