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» Level Shifter Design for Low Power Applications
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73
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DAC
1999
ACM
15 years 10 months ago
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, ...
67
Voted
IROS
2009
IEEE
173views Robotics» more  IROS 2009»
15 years 4 months ago
Biologically inspired compliant control of a monopod designed for highly dynamic applications
— In this paper the compliant low level control of a biologically inspired control architecture suited for bipedal dynamic walking robots is presented. It consists of elastic mec...
Sebastian Blank, Thomas Wahl, Tobias Luksch, Karst...
ICCD
1999
IEEE
115views Hardware» more  ICCD 1999»
15 years 2 months ago
Customization of a CISC Processor Core for Low-Power Applications
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong...
ASPDAC
2004
ACM
89views Hardware» more  ASPDAC 2004»
15 years 1 months ago
Predictable design of low power systems by pre-implementation estimation and optimization
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
Wolfgang Nebel
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
15 years 1 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...