Sciweavers

915 search results - page 129 / 183
» Level Shifter Design for Low Power Applications
Sort
View
DAC
2002
ACM
15 years 10 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
15 years 2 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
ISORC
2009
IEEE
15 years 4 months ago
Adding Timing-Awareness to AUTOSAR Basic-Software -- A Component Based Approach
AUTOSAR as specified in its current version fosters timing-constraints at application level to support the development of real-time automotive applications. However, the standard...
Dietmar Schreiner, Markus Schordan, Jens Knoop
VLSID
2009
IEEE
107views VLSI» more  VLSID 2009»
15 years 10 months ago
Temperature Aware Scheduling for Embedded Processors
Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and inc...
Ramkumar Jayaseelan, Tulika Mitra
ESAS
2004
Springer
15 years 3 months ago
Public Key Cryptography in Sensor Networks - Revisited
The common perception of public key cryptography is that it is complex, slow and power hungry, and as such not at all suitable for use in ultra-low power environments like wireless...
Gunnar Gaubatz, Jens-Peter Kaps, Berk Sunar