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» Level Shifter Design for Low Power Applications
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MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
15 years 4 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
CODES
2007
IEEE
15 years 4 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
BMCBI
2006
128views more  BMCBI 2006»
14 years 9 months ago
Rank-statistics based enrichment-site prediction algorithm developed for chromatin immunoprecipitation on chip experiments
Background: High density oligonucleotide tiling arrays are an effective and powerful platform for conducting unbiased genome-wide studies. The ab initio probe selection method emp...
Srinka Ghosh, Heather A. Hirsch, Edward A. Sekinge...
FCCM
2000
IEEE
162views VLSI» more  FCCM 2000»
15 years 2 months ago
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
Simplifying the programming models is paramount to the success of reconfigurable computing. We apply the principles of object-oriented programming to the design of stream archite...
Oskar Mencer, Heiko Hübert, Martin Morf, Mich...
ASPLOS
2004
ACM
15 years 3 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...