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» Level Shifter Design for Low Power Applications
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DAC
2005
ACM
14 years 11 months ago
Sign bit reduction encoding for low power applications
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
DAC
2001
ACM
15 years 10 months ago
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
Haris Lekatsas, Jörg Henkel
PIMRC
2008
IEEE
15 years 4 months ago
Radio-Triggered Wake-ups with Addressing Capabilities for extremely low power sensor network applications
Sensor network applications are generally characterized by long idle durations and intermittent communication patterns. The traffic loads are typically so low that overall idle d...
Junaid Ansari, Dmitry Pankin, Petri Mähö...
PATMOS
2000
Springer
15 years 1 months ago
Dynamic Memory Design for Low Data-Retention Power
Abstract. The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical oper...
Joohee Kim, Marios C. Papaefthymiou
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
15 years 2 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...