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» Level Shifter Design for Low Power Applications
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CDES
2006
240views Hardware» more  CDES 2006»
14 years 11 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
DAC
2005
ACM
15 years 10 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
MM
2005
ACM
157views Multimedia» more  MM 2005»
15 years 3 months ago
Chameleon: application level power management with performance isolation
In this paper, we present Chameleon—an application-level power management approach for reducing energy consumption in mobile processors. Our approach exports the entire responsi...
Xiaotao Liu, Prashant J. Shenoy, Mark D. Corner
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 1 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
DCC
2000
IEEE
15 years 2 months ago
Arithmetic Coding for Low Power Embedded System Design
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
Haris Lekatsas, Wayne Wolf, Jörg Henkel