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» Level Shifter Design for Low Power Applications
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ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
15 years 2 months ago
Instruction level power model of microcontrollers
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
C. Chakrabarti, D. Gaitonde
ASAP
2004
IEEE
115views Hardware» more  ASAP 2004»
15 years 1 months ago
A Low-Power Carry Skip Adder with Fast Saturation
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
Michael J. Schulte, Kai Chirca, John Glossner, Hao...
ICCAD
2002
IEEE
80views Hardware» more  ICCAD 2002»
15 years 6 months ago
Minimizing power across multiple technology and design levels
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
Takayasu Sakurai
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
15 years 2 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 4 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...