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CORR
2010
Springer
196views Education» more  CORR 2010»
14 years 9 months ago
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computin...
H. G. Rangaraju, U. Venugopal, K. N. Muralidhara, ...
ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
15 years 6 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young
FPL
2008
Springer
91views Hardware» more  FPL 2008»
14 years 11 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
ISLPED
2003
ACM
96views Hardware» more  ISLPED 2003»
15 years 3 months ago
Effective graph theoretic techniques for the generalized low power binding problem
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
Azadeh Davoodi, Ankur Srivastava
FPL
2005
Springer
140views Hardware» more  FPL 2005»
15 years 3 months ago
A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow
The aim of the PhD thesis is the development of systematic methodologies both for hardware and software level for designing low-energy and performance efficient reconfigurable sys...
K. Siozios, Dimitrios Soudris, Adonios Thanailakis