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» Level Shifter Design for Low Power Applications
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ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
15 years 2 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
HOTOS
1999
IEEE
15 years 2 months ago
The Case for Higher-Level Power Management
Reducing the energy consumed in the use of computing devices is becoming a major design challenge. While the problem obviously must be addressed with improved low-level technology...
Carla Schlatter Ellis
DAC
1999
ACM
15 years 2 months ago
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 1 months ago
Low Static-Power Frequent-Value Data Caches
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
Chuanjun Zhang, Jun Yang 0002, Frank Vahid
ISCAS
2003
IEEE
156views Hardware» more  ISCAS 2003»
15 years 3 months ago
GNOMES: a testbed for low power heterogeneous wireless sensor networks
Continuing trends in sensor, semiconductor and communication systems technology (smaller, faster, cheaper) make feasible very dense networks of fixed and mobile wireless devices ...
Erik Welsh, Walt Fish, J. Patrick Frantz