915 search results - page 40 / 183 » Level Shifter Design for Low Power Applications |
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
DATE
1999
IEEE
15 years 2 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
ERSA
2007
14 years 11 months ago
2007
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...