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» Level Shifter Design for Low Power Applications
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ESAS
2004
Springer
15 years 3 months ago
Secure AES Hardware Module for Resource Constrained Devices
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
Elena Trichina, Tymur Korkishko
BSN
2009
IEEE
160views Sensor Networks» more  BSN 2009»
15 years 4 months ago
BSN Simulator: Optimizing Application Using System Level Simulation
—A biomonitoring application running on wireless BAN has stringent timing and energy requirements. Developing such applications therefore presents unique challenges in both hardw...
Ioana Cutcutache, Thi Thanh Nga Dang, Wai Kay Leon...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
WCNC
2008
IEEE
15 years 4 months ago
Novel Ultra Wideband Low Complexity Ranging Using Different Channel Statistics
—UWB technology can reach centimetre level ranging and positioning accuracy in LOS propagation when time of arrival techniques are used. However, in a real positioning system, th...
Giovanni Bellusci, Gerard J. M. Janssen, Junlin Ya...
CASES
2005
ACM
14 years 11 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh