915 search results - page 50 / 183 » Level Shifter Design for Low Power Applications |
IPSN
2007
Springer
15 years 4 months ago
2007
Springer
We present SPOT, a scalable power observation tool that enables in situ measurement of nodal power and energy over a dynamic range exceeding four decades or a temporal resolution ...
ISLPED
1998
ACM
15 years 2 months ago
1998
ACM
Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...