Sciweavers

915 search results - page 51 / 183
» Level Shifter Design for Low Power Applications
Sort
View
ICC
2009
IEEE
136views Communications» more  ICC 2009»
14 years 7 months ago
Maximizing the Sum Rate in Symmetric Networks of Interfering Links
We consider the power optimization problem of maximizing the sum rate of a symmetric network of interfering links in Gaussian noise. All transmitters have an average transmit power...
Sibi Raj Bhaskaran, Stephen V. Hanly, Nasreen Badr...
ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
15 years 3 months ago
Low energy asynchronous architectures
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
Ilya Obridko, Ran Ginosar
ASPLOS
2000
ACM
15 years 2 months ago
Thread Level Parallelism and Interactive Performance of Desktop Applications
Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear f...
Krisztián Flautner, Richard Uhlig, Steven K...
CLUSTER
2007
IEEE
15 years 1 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
CASES
2007
ACM
15 years 1 months ago
Application driven embedded system design: a face recognition case study
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
Karthik Ramani, Al Davis