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JEC
2006
88views more  JEC 2006»
14 years 9 months ago
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
John Oliver, Ravishankar Rao, Diana Franklin, Fred...
KES
2005
Springer
15 years 3 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee
ICRA
2009
IEEE
147views Robotics» more  ICRA 2009»
15 years 4 months ago
Milligram-scale high-voltage power electronics for piezoelectric microrobots
— Piezoelectric actuators can achieve high efficiency and power density in very small geometries, which shows promise for microrobotic applications, such as flapping-wing robot...
Michael Karpelson, Gu-Yeon Wei, Robert J. Wood
DSN
2000
IEEE
15 years 2 months ago
A Low Latency, Loss Tolerant Architecture and Protocol for Wide Area Group Communication
Group communication systems are proven tools upon which to build fault-tolerant systems. As the demands for fault-tolerance increase and more applications require reliable distrib...
Yair Amir, Claudiu Danilov, Jonathan Robert Stanto...
JSA
2010
158views more  JSA 2010»
14 years 4 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...