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» Level Shifter Design for Low Power Applications
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ARITH
2005
IEEE
15 years 3 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
DAC
2002
ACM
15 years 11 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
15 years 3 months ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
IJHR
2007
104views more  IJHR 2007»
14 years 10 months ago
Upper Limb Powered Exoskeleton
—An exoskeleton is an external structural mechanism with joints and links corresponding to those of the human body. With applications in rehabilitation medicine and virtual reali...
Jacob Rosen, Joel C. Perry
ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
15 years 7 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...