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» Level Shifter Design for Low Power Applications
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DAC
2008
ACM
15 years 11 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
15 years 10 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
DATE
2007
IEEE
93views Hardware» more  DATE 2007»
15 years 4 months ago
Minimum-energy LDPC decoder for real-time mobile application
— This paper presents a low-power real-time decoder that provides constant-time processing of each frame using dynamic voltage and frequency scaling. The design uses known capaci...
Weihuang Wang, Gwan Choi
IPPS
2006
IEEE
15 years 4 months ago
Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications
Recently, under a fixed power budget, asymmetric multiprocessors (AMP) have been proposed to improve the performance of multi-threaded applications compared to symmetric multiproc...
Ryan E. Grant, Ahmad Afsahi
ASPLOS
2006
ACM
15 years 1 months ago
Accurate and efficient regression modeling for microarchitectural performance and power prediction
We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a...
Benjamin C. Lee, David M. Brooks