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» Level Shifter Design for Low Power Applications
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ISLPED
2009
ACM
184views Hardware» more  ISLPED 2009»
15 years 4 months ago
Online work maximization under a peak temperature constraint
Increasing power densities and the high cost of low thermal resistance packages and cooling solutions make it impractical to design processors for worst-case temperature scenarios...
Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
15 years 1 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton
IPPS
2000
IEEE
15 years 2 months ago
Predicting Performance on SMPs. A Case Study: The SGI Power Challenge
We study the issue of performance prediction on the SGIPower Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention ...
Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andre...
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 1 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
CCGRID
2001
IEEE
15 years 1 months ago
Data Staging Effects in Wide Area Task Farming Applications
Recent advances in computing and communication have given rise to the computational grid notion. The core of this computing paradigm is the design of a system for drawing compute ...
Wael R. Elwasif, James S. Plank, Richard Wolski