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» Levels of Description: A Novel Approach to Dynamical Hierarc...
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SIGPLAN
2008
15 years 1 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
130
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TJS
2002
136views more  TJS 2002»
15 years 1 months ago
A Virtual Test Facility for the Simulation of Dynamic Response in Materials
The Center for Simulating Dynamic Response of Materials at the California Institute of Technology is constructing a virtual shock physics facility for studying the response of vari...
Julian Cummings, Michael Aivazis, Ravi Samtaney, R...
CACM
1999
113views more  CACM 1999»
15 years 1 months ago
Object-oriented Abstractions for Distributed Programming
ion suffices ("decide which type you want and provide a full set of operations for each type"). If the application domain is, say, the administration of a university, the...
Rachid Guerraoui, Mohamed Fayad
DAC
2002
ACM
16 years 2 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
CONEXT
2009
ACM
15 years 3 months ago
Exploiting dynamicity in graph-based traffic analysis: techniques and applications
Network traffic can be represented by a Traffic Dispersion Graph (TDG) that contains an edge between two nodes that send a particular type of traffic (e.g., DNS) to one another. T...
Marios Iliofotou, Michalis Faloutsos, Michael Mitz...