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ISSRE
2008
IEEE
15 years 11 months ago
Finding Faults: Manual Testing vs. Random+ Testing vs. User Reports
The usual way to compare testing strategies, whether theoretically or empirically, is to compare the number of faults they detect. To ascertain definitely that a testing strategy...
Ilinca Ciupa, Bertrand Meyer, Manuel Oriol, Alexan...
ISVLSI
2008
IEEE
126views VLSI» more  ISVLSI 2008»
15 years 11 months ago
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Run...
MICRO
2008
IEEE
121views Hardware» more  MICRO 2008»
15 years 11 months ago
Temporal instruction fetch streaming
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
Michael Ferdman, Thomas F. Wenisch, Anastasia Aila...
PDP
2008
IEEE
15 years 11 months ago
Type Safe Algorithmic Skeletons
This paper addresses the issue of type safe algorithmic skeletons. From a theoretical perspective we contribute by: formally specifying a type system for algorithmic skeletons, an...
Denis Caromel, Ludovic Henrio, Mario Leyton
117
Voted
ASAP
2007
IEEE
169views Hardware» more  ASAP 2007»
15 years 11 months ago
Reduced Delay BCD Adder
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
A. A. Bayrakci, A. Akkas