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116
Voted
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
15 years 10 months ago
Massively multi-topology sizing of analog integrated circuits
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
Pieter Palmers, Trent McConaghy, Michiel Steyaert,...
126
Voted
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
15 years 10 months ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...
112
Voted
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
15 years 10 months ago
Gate sizing for large cell-based designs
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
Stephan Held
114
Voted
DSN
2009
IEEE
15 years 10 months ago
VNsnap: Taking snapshots of virtual networked environments with minimal downtime
A virtual networked environment (VNE) consists of virtual machines (VMs) connected by a virtual network. It has been adopted to create “virtual infrastructures” for individual...
Ardalan Kangarlou, Patrick Eugster, Dongyan Xu
WCRE
2009
IEEE
15 years 10 months ago
NTrace: Function Boundary Tracing for Windows on IA-32
—For a long time, dynamic tracing has been an enabling technique for reverse engineering tools. Tracing can not only be used to record the control flow of a particular component...
Johannes Passing, Alexander Schmidt, Martin von L&...