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2006
IEEE
15 years 9 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
DASFAA
2006
IEEE
141views Database» more  DASFAA 2006»
15 years 9 months ago
Dataspaces: A New Abstraction for Information Management
straction for Information Management Michael Franklin University of California, Berkeley Alon Halevy Google Inc. and U. Washington David Maier Portland State University The develo...
Alon Y. Halevy, Michael J. Franklin, David Maier
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
15 years 9 months ago
Enabling fine-grain leakage management by voltage anchor insertion
Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a s...
Pietro Babighian, Luca Benini, Alberto Macii, Enri...
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
15 years 9 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 9 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...